Exemplary embodiments of the present invention relate generally to a stack package, and more particularly, to a stack package including through-silicon vias (TSVs), which can enable a chip to be easily selected, and a method for selecting a chip in a stack package.
Small sized, high performing electronic products require ultra-miniaturized, high memory capacity semiconductor memory devices. To improve the storage capacity, a semiconductor memory device can be made with a semiconductor chip that is more highly integrated and in a semiconductor package having a plurality of chips. Packaging is generally considered to be more effective and less costly to increase storage capacity as compared to improving the degree of high integration in the semiconductor chip.
A multi-chip package includes a plurality of semiconductor chips, and the semiconductor chips are mounted horizontally or vertically in a semiconductor package. To mount more semiconductor chips in a semiconductor package, a stack type multi-chip package in which semiconductor chips are mounted vertically is used. Furthermore, through-silicon via (TSV) is one of the enabling technologies for the stack type multi-chip package with high density and high performance.
FIG. 1 is a perspective view of a known stack package, FIG. 2 is a cross-sectional view of the part A (the chip selection pad part) of FIG. 1, and FIG. 3 is a plan view showing an example of connecting chip selection pads using redistribution layers.
Referring to FIG. 1, semiconductor chips 20, 30, 40 and 50 are stacked on a substrate 10 and are connected with one another by means of through-silicon vias (TSVs) 24, 34, 44 and 54. A Vcc pad 12 and a Vss pad 14 are formed on the substrate 10, and various I/O pads are formed on the respective chips 20, 30, 40 and 50. Some of the I/O pads serve as chip selection pads 22, 32, 42 and 52 used for selecting chips. In the case where the same chips 20, 30, 40 and 50 are stacked using the through-silicon vias 24, 34, 44 and 54, since the chip selection pads 22, 32, 42 and 52 are formed at the same vertical position, chip selection cannot be implemented using the through-silicon vias 24, 34, 44 and 54. Accordingly, redistribution layers 26, 36, 46 and 56 are formed on the respective chip selection pads 22, 32, 42 and 52 to be connected with through-silicon vias 28, 38, 48 and 58 which are formed at different positions. However, since the redistribution layers 26, 36, 46 and 56 of the stacked chips 20, 30, 40 and 50 have different patterns, processing costs increase and difficulties exist in administrating processes.
FIG. 4 is a perspective view showing a method for selecting a chip using wires. Referring to FIG. 4, in the case where the same semiconductor chips 20, 30, 40 and 50 are stacked, since chip pads are formed at the same positions, semiconductor chips 20, 30, 40 and 50 are stacked in a step-like shape, and chip selection pads 22, 32, 42 and 52 are connected with a Vcc pad 12 and a Vss pad 14 using wires W so as to be capable of applying chip selection signals to the semiconductor chips 20, 30, 40 and 50. Nevertheless, wire bonding for chip selection increases the thickness of a package and the lengths of the wires W increase depending upon the number of semiconductor chips, causing signal delay and degrading the structural reliability of a package.